1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device and a related error checking and correction (ECC) method. In particular, embodiments of the invention relate to a multi-layer semiconductor memory device having an ECC engine and a related ECC method performed using a multi-layer semiconductor memory device.
2. Description of Related Art
Dynamic random access memory (DRAM), non-volatile flash memory, and high-speed static random access memory (SRAM) have become more highly integrated through the use of resistance memory devices such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and the like. Thus, resistance memory devices are considered next generation memory. The ability to reduce chip size for conventional memory devices is limited by the transistors that are used as switching elements in those devices. However, there is increasing demand for resistance memory devices having relatively high integration densities and relatively low power consumption.
Therefore, a multi-layer semiconductor memory 100, as illustrated in FIG. 1, has been provided. Referring to FIG. 1, multi-layer semiconductor memory 100 comprises first through third memory cell arrays L1˜L3 disposed on a silicon substrate SUB. However, embodying a memory device that uses transistors as switching elements in the form of multi-layer semiconductor memory 100 is difficult. Since transistors are formed on silicon substrate SUB, forming transistors in second and third memory cell arrays L2 and L3 is more difficult.
Therefore, an RRAM including a non-ohmic device is embodied in the form of a multi-layer semiconductor memory device. FIG. 2 is a schematic view of a cell structure of a conventional bi-directional RRAM. Referring to FIG. 2, the bi-directional RRAM includes a non-ohmic device and a resistance variable device. In the RRAM, data is written using resistance-value variations of the resistance variable device. The resistance variable device includes a resistance variable substance disposed between first and second electrodes.
The resistance value of the resistance variable substance varies in accordance with an applied voltage or an applied current. In unidirectional RRAM, the resistance value varies in accordance with the magnitude of the applied voltage or applied current. On the other hand, in the bi-directional RRAM, the resistance value varies in accordance with the magnitude and the direction of the applied voltage or applied current.
The bi-directivity described above is implemented in the bi-directional RRAM illustrated in FIG. 2 by including the non-ohmic device in the bi-directional RRAM. The non-ohmic device is in a high-resistant state in a predetermined voltage range of −3V˜3V. Accordingly, a current is not applied to the resistance variable device.
On the other hand, the non-ohmic device is in a low-resistant state outside of the predetermined voltage range of −3V˜3V. Accordingly, a current is applied to the resistance variable device outside of that range. U.S. Pat. Nos. 6,909,632 and 6,753,561 disclose a bi-directional RRAM including a non-ohmic device and a resistance variable device in more detail.
FIG. 3 is a graph illustrating cell characteristics of the conventional bi-directional RRAM illustrated in FIG. 2. Referring to FIGS. 2 and 3, when a writing voltage VW of 6V is applied to the resistance variable substance, a corresponding cell has a first resistance. On the other hand, when a writing voltage −VW of −6V is applied to the resistance variable substance, a corresponding cell has a second resistance.
In the bi-directional RRAM, a data value of “1” can be stored when a cell has the first resistance and a data value of “0” can be stored when a cell has the second resistance. That is, in the bi-directional RRAM, the data values “1” and “0” can be written using the writing voltages VW and −VW, wherein the magnitudes of the writing voltages VW and −VW, applied at respective ends of the cell, are the same, but the polarities are different.
FIGS. 4A and 4B are schematic views illustrating write operations in which data is written to a cell of the conventional bi-directional RRAM illustrated in FIG. 2. Referring to FIG. 4A, the data value “0” is written to a cell (illustrated as a circle in FIG. 4) by applying 3V to a word line WL and −3V to a bit line BL. On the other hand, the data value “1” is written to the cell by applying −3V to the word line WL and 3V to the bit line BL. In each of those write operations, 0V is applied to the unselected word line WL′ and the unselected bit line BL′.
Referring to FIG. 4B, the data value “0” is written to a cell by applying 6V to a word line WL, 0V to a bit line BL, and 3V to both unselected word line WL′ and unselected bit line BL′. On the other hand, the data value “1” is written to the cell by applying 0V to the word line WL, −6V to the bit line BL, and −3V to both the unselected word line WL′ and the unselected bit line BL′.
However, when data is written by applying writing voltages VW and −VW (VW=6V, −VW=−6V) to a word line WL or a bit line BL as shown in FIG. 4B, the voltages of an unselected word line WL′ and an unselected bit line BL′ change in accordance with the data value being written. Thus, writing data by applying ½ writing voltages ½VW and −½VW (½VW=3V, −½VW=−3V) to the word line WL and the bit line BL, respectively, as shown in FIG. 4A, is more efficient.
In addition, layers of RRAM cells (wherein each cell comprises a non-ohmic device) may be readily stacked. Also, the operation of an RRAM device having cells that each comprise a non-ohmic device may be readily controlled, and such an RRAM device can be implemented as a multi-layer memory.
In addition to reducing chip size of a semiconductor memory device, increasing the yield of a semiconductor memory device is also an important consideration. However, weak cells are likely to be produced when there is a geometric increase in capacity of a semiconductor memory device.
A semiconductor memory device comprises a relatively large number of memory cells. However, when there is a defective memory cell among the memory cells of the semiconductor memory device, the device will not operate properly. Therefore, more effective detection and correction of a weak cell are critical issues in increasing the yield of a semiconductor memory device.
To address this issue, many semiconductor memory devices include a redundancy circuit for replacing a weak cell with a redundant cell to increase the yield. Generally, the redundancy circuit drives a redundancy memory cell block having aligned redundant rows and columns and replaces the weak cell with a redundancy cell of the redundancy memory cell block (i.e., uses a redundancy cell of the redundancy memory cell block in place of the weak cell). That is, if an address signal designating the weak cell is input, the redundancy memory cell is selected instead of the weak cell.
However, the redundancy circuit establishes the number of memory cells that can be replaced with redundancy cells in advance and assigns the memory cells near the memory cell block. Thus, if the number of weak cells exceeds the maximum number of redundancy cells, less than all of the weak cells can be replaced. In that case, the semiconductor memory device is finally determined to be defective and revoked. Therefore, having a limited number of redundancy cells limits increasing the yield of a semiconductor memory device.
Alternatively, a semiconductor memory device may have an error checking and correction (ECC) function to increase the yield of the semiconductor memory device.
FIG. 5 is a block diagram of a semiconductor memory device 500 including an ECC engine 540. Referring to FIG. 5, a memory cell array 520 of semiconductor memory device 500 including ECC engine 540 is divided into a payload data region 522 storing payload data NDTA and a parity data region 524 storing parity data PDTA. ECC engine 540 stores parity data PDTA (which corresponds to payload data NDTA) when payload data NDTA is written onto semiconductor memory device 500. In addition, semiconductor memory device 500 performs an ECC operation using parity data PDTA when payload data NDTA is read from semiconductor memory device 500.
Parity data PDTA is established so that the result of performing an exclusive OR (EOR) operation on payload data NDTA and parity data PDTA (i.e., an ECC operation) always has a previously determined value. For example, the previously determined value may be “1” in an odd parity system or “0” in an even parity system. If the result of an ECC operation is a value other than the previously determined value, then ECC engine 540 determines that payload data NDTA is faulty data, corrects payload data NDTA, and outputs the corrected payload data NDTA.
The number of bits of parity data used for the ECC function is selected depending on the ECC performance required. The greater the number of bits of parity data used for error correction, the more errors can be corrected. However, cell overhead increases as the number of bits of parity data used increases.
FIG. 6 is a table illustrating the relationship between the number of bits of payload data and the number of bits of parity data. Referring to FIG. 6, a hamming code is used to correct a 1-bit error. Among 8 data bits, 4 bits of parity data is necessary to correct the 1-bit error. So, for example, 0.5 GB of parity data would be required when storing 1 GB of payload data.
Therefore, an increase in memory size (i.e., cell overhead) occurs due to the amount of data storage space needed for parity data in order to implement the ECC function. Although an increase in the number of bits of parity data can reduce cell overhead, accurate error detection is limited. Moreover, referring to FIG. 5, payload data region 522 and parity data region 524 are disposed on the same plane in the conventional memory device.